Referring to FIG. 1, a conventional JTAG boundary scan control signal routing of an application specific integrated circuit (ASIC) 10 is shown. The JTAG signal routing of the ASIC 10 is buffered in a tree structure. The starting point for the tree is typically located somewhere in the center region of the die. In some instances the JTAG boundary scan gates can be placed elsewhere manually. From the starting point the trees fan out to all different sides of the ASIC 10. Therefore, the ASIC 10 will have JTAG boundary scan signal buffers all over the die. Also, routes will go through the center of the die. Because there are several control nets which can go to each I/O cell (not shown, surrounding the ASIC 10), uncontrolled routing occurs and increases congestion problems.
Conventional approaches manually place JTAG boundary scan gates before routing in an attempt to reduce unnecessary routing. However, current netlists which go into layout do not contain sufficient buffering of the high fanout JTAG boundary scan control nets. Therefore, insertion of buffers is done by layout tools based on distances, maximum ramp times or similar requirements, but never driven by the order of I/Os. The result of the buffering is a tree structure across the die. Furthermore, each design has to be handled individually, since no common solution exists.
Conventional boundary scan methodologies are used to test I/Os (i.e., input/output circuitry to connect a chip to the external world) on silicon. There is a set of required boundary scan cells for every set of I/Os to be tested. The boundary scan cells can be placed by a placement tool (or manually in front of the respective I/Os to avoid any timing issues). Flip flops (not shown) in the scan chain are then connected together as a register chain. The placement tool can place the boundary scan cells far away from the respective I/Os, particularly when memories (or other dedicated blocks) are placed in front of the I/Os.
Referring to FIG. 2, a circuit 20 is shown illustrating a conventional boundary scan connection with the boundary scan cells 22a–22n outside the I/O cells 24a–24n. Trying to connect the boundary scan cells 22a–22n, which are scattered over the entire die, can cause timing problems. Since the boundary scan flip flops are connected in a chain, routing issues cause severe hold time violations, thereby causing the chain to fail. However, placing the boundary scan cells 22a–22n manually is very time consuming (there typically exist hundreds of cells in a single device). For example, the manual placement process can take a number of days in a standard size design. Additionally, there is a clock tree at the top level to clock the boundary scan flip flops. Therefore, managing a reasonable skew at chip level is challenging, time consuming and area consuming. Furthermore, since more I/O cells are continually being added inside the I/O devices, timing modeling of the I/O devices need to be constantly updated.